Integrated circuits (ICs) can be implemented to perform a variety of functions. Some ICs can be programmed to perform specified functions. One example of an IC that can be programmed is a field programmable gate array (FPGA). An FPGA typically includes programmable circuitry implemented as an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
In some cases, a programmable IC also includes an embedded processor system. The processor system can include a processor (e.g., central processing unit or “CPU”) coupled to memory. The memory is capable of storing program code and/or data. The processor is capable of accessing the memory to execute the program code and operate on the data. Further, the processor system is capable of interacting with circuitry and/or other systems implemented using the programmable circuitry of the programmable IC. A programmable IC of this variety is also called a System-on-Chip (SoC).
One benefit of using an SoC is that a task that can be implemented in software, e.g., as an executable process performed by the processor system, can be offloaded to a circuit implemented in the programmable circuitry. The circuit is functionally equivalent to program code that can be executed by the processor system to perform the task. The circuit, however, often provides one or more benefits that are not attainable through execution of the program code by the processor system. The benefit(s) can include faster operation, reduced power consumption, redundancy, etc. Despite the fact that the benefits may or may not include faster operation, the circuit is often referred to as a “hardware accelerator”.
Hardware accelerators are often made available to users as cores. In order to utilize a hardware accelerator, an application executed by the processor system must be able to invoke the hardware accelerator in the programmable circuitry of the SoC. Available techniques for instantiating a hardware accelerator are unable to handle complexities that arise when multiple copies of a hardware accelerator are desired, when the different copies of the hardware accelerator have different configurations, and/or when the hardware accelerator is a multi-function accelerator.